`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:29:35 04/05/2011 
// Design Name: 
// Module Name:    SignExtend 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module SignExtend(a, y);
    input [7:0] a;
    output [15:0] y;
	 
	 wire [15:0] y;
	 assign y[7:0] = a[7:0];
	 assign y[8] = a[7];
	 assign y[9] = a[7];
	 assign y[10] = a[7];
	 assign y[11] = a[7];
	 assign y[12] = a[7];
	 assign y[13] = a[7];
	 assign y[14] = a[7];
	 assign y[15] = a[7];


endmodule
